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IP4770/71/72CZ16
VGA/video interface with integrated buffers, ESD protection and integrated termination resistors
Rev. 01 -- 25 October 2006 Product data sheet
1. General description
The IP4770CZ16, IP4771CZ16, IP4772CZ16 is connected between the VGA/DVI interface and the video graphics controller and includes level shifting for the DDC signals, buffering for the SYNC lines as well as high-level ESD protection diodes for the RGB signal lines. The level shifting functions are required when the DDC controller operates at a lower supply voltage than the monitor. To use this level shifting function the gates of the two N-channel MOSFETs have to be connected to the supply rail of the DDC transceivers. Buffering for the SYNC signals is provided by two non-inverting buffers, which accept TTL input levels and convert these to CMOS compliant output levels between pins VCC(SYNC) and GND. The IP4770CZ16 and IP4771CZ16 contain the formerly external termination resistors, which are typically required for the HSYNC and VSYNC lines of the video interface:
* IP4770CZ16: Rsync = 55 * IP4771CZ16: Rsync = 65 * IP4772CZ16: Rsync =10 to allow termination of the SYNC lines
All RGB I/Os are protected by a special diode configuration offering a low line capacitance of 4 pF (maximum) only to provide protection to downstream components for ESD voltages as high as 8 kV contact discharge according to IEC 61000-4-2, level 4 standard.
2. Features
I Integrated high-level ESD protection, buffering, SYNC signal impedance matching and level shifting I Terminal connections with integrated rail-to-rail clamping diodes with downstream ESD protection of 8 kV according to IEC 61000-4-2, level 4 standard I Backflow protection on DDC lines I Drivers for HSYNC and VSYNC lines I Bidirectional level shifting N-channel FETs available for DDC clock and DDC data channels I Integrated impedance matching resistors on SYNC lines I Line capacitance < 4 pF per channel I Lead-free package and RoHS compliant
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
3. Applications
I To terminate and to buffer channels, to reduce EMI/RFI and to provide downstream ESD protection for: N VGA interfaces including DDC channels N Desktop and notebooks PCs N Graphics cards N Set top boxes
4. Ordering information
Table 1. Ordering information Package Name IP4770CZ16 IP4771CZ16 IP4772CZ16 SSOP16 Description plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm Version SOT519-1 Type number
5. Functional diagram
VCC(VIDEO) VCC(SYNC)
Rterm
SYNC_IN1
Rterm
SYNC_OUT1
VIDEO_1 VIDEO_2
SYNC_IN2
SYNC_OUT2
VIDEO_3
DDC_OUT1 DDC_OUT2 VCC(SYNC) VCC(DDC) BYP
DDC_IN1 DDC_IN2
001aae818
IP4772CZ16: Rsync = Rbuffer and Rterm = 0 .
Fig 1. Functional diagram
IP4770CZ16_4771_4772_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 25 October 2006
2 of 11
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
6. Pinning information
6.1 Pinning
VCC(SYNC) VCC(VIDEO) VIDEO_1 VIDEO_2 VIDEO_3 GND VCC(DCC) BYP
1 2 3 4 5 6 7 8
001aae809
16 SYNC_OUT2 15 SYNC_IN2 14 SYNC_OUT1
IP4770CZ16 IP4771CZ16 IP4772CZ16
13 SYNC_IN1 12 DDC_OUT2 11 DDC_IN2 10 DDC_IN1 9 DDC_OUT1
Fig 2. Pin configuration
6.2 Pin description
Table 2. Symbol VCC(SYNC) VCC(VIDEO) VIDEO_1 VIDEO_2 VIDEO_3 GND VCC(DDC) BYP Pin description Pin Description 1 2 3 4 5 6 7 8 supply voltage for SYNC_1 and SYNC_2 level shifter and their connected ESD protections supply voltage for VIDEO_1, VIDEO_2 and VIDEO_3 protection circuits video signal ESD protection channel 1 video signal ESD protection channel 2 video signal ESD protection channel 3 ground supply voltage for DDC_1 and DDC_2 level shifter N-FET gates this input is used to connect an external 0.2 F bypass capacitor to increase ESD withstand voltage rating for the DDC outputs (8 kV with capacitor or 4 kV without capacitor) DDC signal output 1; connected to the video connector side of one of the SYNC lines DDC signal input 1; connected to the VGA controller side of one of the SYNC lines DDC signal input 2; connected to the VGA controller side of one of the SYNC lines DDC signal output 2; connected to the video connector side of one of the SYNC lines SYNC signal input 1; connected to the VGA controller side of one of the SYNC lines SYNC signal output 1; connected to the video connector side of one of the SYNC lines SYNC signal input 2; connected to the VGA controller side of one of the SYNC lines SYNC signal output 2; connected to the video connector side of one of the SYNC lines
(c) NXP B.V. 2006. All rights reserved.
DDC_OUT1 DDC_IN1 DDC_IN2 DDC_OUT2 SYNC_IN1
9 10 11 12 13
SYNC_OUT1 14 SYNC_IN2 15
SYNC_OUT2 16
IP4770CZ16_4771_4772_1
Product data sheet
Rev. 01 -- 25 October 2006
3 of 11
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to ground (GND). Symbol VESD Parameter electrostatic discharge voltage Conditions IEC 61000-4-2; pins VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SYNC_OUT2, DDC_OUT1, DDC_OUT2 level 4; contact level 4; air discharge IEC 61000-4-2; all other pins level 1; contact level 1; air discharge VCC(VIDEO) VCC(DDC) VCC(SYNC) VI(VIDEO_1) VI(VIDEO_2) VI(VIDEO_3) VI(DDC_IN1) VI(DDC_IN2) VI(SYNC_IN1) VI(SYNC_IN2) VO(DDC_OUT1) VO(DDC_OUT2) Ptot Tstg
[1]
[1]
Min
Max
Unit
-8 -15
+8 +15
kV kV
-2 -2 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
+2 +2 5.5 5.5 5.5 VCC(VIDEO) VCC(VIDEO) VCC(VIDEO) VCC(DDC) VCC(DDC) VCC(SYNC) VCC(SYNC) VCC(DDC) VCC(DDC) 500 +125
kV kV V V V V V V V V V V V V mW C
video supply voltage data display channel supply voltage synchronization supply voltage input voltage on pin VIDEO_1 input voltage on pin VIDEO_2 input voltage on pin VIDEO_3 input voltage on pin DDC_IN1 input voltage on pin DDC_IN2 input voltage on pin SYNC_IN1 input voltage on pin SYNC_IN2 output voltage on pin DDC_OUT1 output voltage on pin DDC_OUT2 total power dissipation storage temperature Tamb = 25 C
-55
Pins BYP, VCC(VIDEO) and VCC(SYNC) must be bypassed to ground (pin GND) via a low-impedance ground plane with 0.22 F, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the pins VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SYNC_OUT2, DDC_OUT1, DDC_OUT2 and GND. The bypass capacitor at pin BYP can be omitted. In this case the maximum ESD level for DDC_OUT1 and DDC_OUT2 pins is reduced to 4 kV.
IP4770CZ16_4771_4772_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 25 October 2006
4 of 11
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
8. Recommended operating conditions
Table 4. Symbol Toper Recommended operating conditions Parameter operating temperature Conditions Min -40 Typ Max +85 Unit C
9. Characteristics
Table 5. Sync circuit characteristics VCC(SYNC) = 5 V; Tamb = 25 C; unless otherwise specified. Symbol ICC(SYNC) Parameter supply current on pin VCC(SYNC) SYNC input at 3 V Input: pins SYNC_IN1 and SYNC_IN2 VIH VIL VOH VOL Rsync HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage synchronization resistance IOH = 1 mA IP4772CZ16; IOH = 24 mA IOL = 1 mA IP4772CZ16; IOL = 24 mA IP4770CZ16 IP4771CZ16 IP4772CZ16 Sync channel tPLH tPHL tr(o) tf(o) LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay output rise time output fall time CL = 50 pF; tr and tf 5 ns CL = 50 pF; tr and tf 5 ns CL = 50 pF; tr and tf 5 ns CL = 7 pF; tr and tf 5 ns CL = 50 pF; tr and tf 5 ns CL = 7 pF; tr and tf 5 ns Protection diode IL(r) VBRzd VFd
[1] [2] [3] [4]
[4] [4] [2] [2] [3]
Conditions
[1] [1]
Min 2.0 4.85 2.0 6 -
Typ 55 65 10 4 1.5 4 1.5 0.7
Max 50 2 0.6 0.15 0.8 12 12 1 9 -
Unit A mA V V V V V V ns ns ns ns ns ns A V V
Supply: pin VCC(SYNC)
Output: pins SYNC_OUT1 and SYNC_OUT2
reverse leakage current Zener diode breakdown voltage diode forward voltage
SYNC outputs unloaded. Rsync = Rterm + Rbuffer. Rsync = Rbuffer because Rterm = 0 .
per channel; V = 3.0 V I = 1 mA IF = 1 mA
This parameter is guaranteed by design and characterization.
IP4770CZ16_4771_4772_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 25 October 2006
5 of 11
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
Table 6. Video circuit characteristics VCC(VIDEO) = 5 V; Tamb = 25 C; unless otherwise specified. Symbol ICC(VIDEO) Cch(video) Ii(video) VFd
[1]
Parameter supply current on pin VCC(VIDEO) video channel capacitance video input current diode forward voltage
Conditions static input signals fi = 1 MHz; VI = 2.5 V VI = VCC(VIDEO) or GND IF = 1 mA
[1]
Min -1 -
Typ 0.7
Max 10 4 +1 -
Unit A pF A V
Supply: pin VCC(VIDEO) Video channel: pins VIDEO_1, VIDEO_2 and VIDEO_3
Protection diode
This parameter is guaranteed by design and characterization.
Table 7. Level circuit characteristics VCC(DDC) = 5 V; Tamb = 25 C; unless otherwise specified. Symbol ICC(DDC) N-MOSFET IL(off) Von off-state leakage current on-state voltage drop VCC(DDC) = 2.5 V; VS = GND; IDS = 3 mA per channel; V = 3.0 V I = 1 mA IF = 1 mA
[1]
Parameter supply current on pin VCC(DDC)
Conditions
Min Typ -
Max 10 10 0.18
Unit A A V
Supply: pin VCC(DDC)
Protection diode IL(r) VBRzd VFd
[1]
reverse leakage current Zener diode breakdown voltage diode forward voltage
6 -
0.7
1 9 -
A V V
Input VI(DDC_INx) VCC(DDC)- 0.4 V and output VO(DDC_OUTx) = VCC(DDC) or input VI(DDC_INx) = VCC(DDC) and output VO(DCC_OUTx) VCC(DCC) - 0.4 V.
IP4770CZ16_4771_4772_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 25 October 2006
6 of 11
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
10. Application information
The IP4770CZ16, IP4771CZ16, IP4772CZ16 should be placed as close as possible to the VGA/DVI interface connector. The ESD protection channels VIDEO_1, VIDEO_2 and VIDEO_3 can be connected in any order with RBG signals. The 100 k resistors between the DDC_OUTx channels and VCC_5V are optional. They may be used, if required, to pull-up the DDC_OUTx lines to VCC_5V when no monitor is connected to the VGA connector. Backflow current can flow between pins DDC_OUTx and VCC_5V via these resistors when VCC_5V is powered down.
HSYNC VSYNC
100 k 100 k
EMI-filter VCC_5V VCC(SYNC) SYNC_OUT2 SYNC_IN2 VCCGPIO VCC(DCC) SYNC_IN1 SYNC_OUT1 VCCA_DAC VCC(VIDEO) HSYNC_OUT SYNC_GND VSYNC_OUT
RED
FILTER
VIDEO_1
DCC_OUT2 DCC_IN2
DDC_DATA
GREEN
FILTER
VIDEO_2 DCC_IN1
DIG_GND
BLUE
FILTER 3 x 75
VIDEO_3
DCC_OUT1
DDC_CLK
IP4770CZ16 IP4771CZ16 IP4772CZ16
RED_VIDEO GREEN_VIDEO BLUE_VIDEO DDC_CLK DDC_DATA RED_GND GREEN_GND BLUE_GND
001aae819
Fig 3. Application diagram
IP4770CZ16_4771_4772_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 25 October 2006
7 of 11
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
11. Package outline
SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm SOT519-1
D
E
A X
c y HE vM A
Z 16 9
A2 A1 (A 3) Lp L 1 e bp 8 wM detail X
A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.73 A1 0.25 0.10 A2 1.55 1.40 A3 0.25 bp 0.31 0.20 c 0.25 0.18 D (1) 5.0 4.8 E (1) 4.0 3.8 e 0.635 HE 6.2 5.8 L 1 Lp 0.89 0.41 v 0.2 w 0.18 y 0.09 Z (1) 0.18 0.05 8o o 0
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT519-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 99-05-04 03-02-18
Fig 4. Package outline SOT519-1 (SSOP16)
IP4770CZ16_4771_4772_1 (c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 25 October 2006
8 of 11
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
12. Abbreviations
Table 8. Acronym CMOS DDC DVI EMI ESD FET HSYNC MOSFET PC RFI RGB SYNC TTL VGA VSYNC Abbreviations Description Complementary Metal Oxide Semiconductor Data Display Channel Digital Video Interface ElectroMagnetic Interference ElectroStatic Discharge Field Effect Transistor Horizontal SYNChronization Metal Oxide Semiconductor Field Effect Transistor Personal Computer Radio Frequency Interference Red Green Blue SYNChronization Transistor-Transistor Logic Video Graphics Adapter Vertical SYNChronization
13. Revision history
Table 9. Revision history Release date 20061025 Data sheet status Product data sheet Change notice Supersedes Document ID IP4770CZ16_4771_4772_1
IP4770CZ16_4771_4772_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 25 October 2006
9 of 11
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
IP4770CZ16_4771_4772_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 25 October 2006
10 of 11
NXP Semiconductors
IP4770/71/72CZ16
VGA/video interface with ESD protection
16. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application information. . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact information. . . . . . . . . . . . . . . . . . . . . 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 October 2006 Document identifier: IP4770CZ16_4771_4772_1

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